stock no. 23209-02 09/21/06 advance information 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. ulp memory solutions 670 north mccarthy blvd. suite 220 milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 advance information 4mb ultra-low power asynchronous medical cmos sram 256k x 16 bit overview the n04m1618l1a is an integrated memory device intended for non life-support medical applications. this device is a 4 megabit memory organized as 262,144 words by 16 bits. the device is designed and fabricated using ami semiconductor?s advanced cmos technology with reliability inhancements fo r medical users. the device operates with two chip enable (ce1 and ce2) controls and output enable (oe ) to allow for easy memory expansion. byte controls (ub and lb ) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. this device is optimal for various applications wher e low-power is critical such as battery backup and hand-held devices. the device can operate over a very wide temperature range of -40 o c to +85 o c and is available in a jedec standard bga package features ? dual power supply for lowest power 1.4 to 2.3 volts - vcc 1.4 to 3.6 volts - vccq ? very low standby current 400na at 2.0v and 37 deg c maximum ? very low operating current 0.7ma at 1.8v and 1s (typical) ? low page mode operating current 0.5ma at 1.8v and 1s (typical) ? simple memory control dual chip enables (ce1 and ce2) byte control for independent byte operation output enable (oe ) for memory expansion ? low voltage data retention vcc = 1.2v ? automatic power down to standby mode ? special processing to reduce soft error rate (ser) ? space saving bga package available pin configuration product family part number package type operating temperature power supply (vcc)/(vccq) speed standby current (i sb ), max operating current (icc), max n04m1618l1ab 48 - bga -40 o c to +85 o c 1.4v - 2.3v 1.4v - 3.6v 85ns @ 1.7v 150ns @ 1.4v 10 a3 ma @ 1mhz n04m1618l1at 44 - tsop ii n04m1618l1aw wafer pin one 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 n04m1618l2at tsop lb# oe# a 0 a 1 a 2 ce2 i/o 8 ub# a 3 a 4 ce1# i/o 0 i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 v ss i/o 11 a 17 a 7 i/o 3 v ccq v cc i/o 12 nc a 16 i/o 4 v ss i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 i/o 15 nc a 12 a 13 we# i/o 7 nc a 8 a 9 a 10 a 11 nc 48 pin bga (top) a b c d e f g h 1 2 3 4 5 6 6 x 8 mm a 4 a 3 a 2 a 1 a 0 ce1# i/o 0 i/o 1 i/o 2 i/o 3 vcc vss i/o 15 i/o 14 i/o 13 i/o 12 we# a 16 a 15 a 14 a 13 a 12 a 5 a 6 a 7 oe# ub# lb# i/o 4 i/o 5 i/o 6 i/o 7 vss vccq i/o 11 i/o 10 i/o 9 i/o 8 ce2 a 8 a 9 a 10 a 11 a 17 pin descriptions pin name pin function a 0 -a 17 address inputs we write enable input ce1 , ce2 chip enable input oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 15 data inputs/outputs v cc power v ccq input/output power v ss ground nc not connected
stock no. 23209-02 09/21/06 advance information 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information functional block diagram functional description ce1 ce2 we oe i/o 0 - i/o 7 mode power h x x x high z standby 1 1. when the device is in standby mode, control inputs (we and oe ), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. standby x l x x high z standby 1 standby lhl x 2 2. when we is invoked, the oe input is internally disabled and has no effect on the circuit. data in write 2 active lhhl data out read active l h h h high z active active capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 8pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 8pf control logic decode logic address inputs a 0 - a 17 we oe input/ output mux and buffers i/o 0 - i/o 7 ub lb i/o 8 - i/o 15 address ce1 256k x 16 memory array
stock no. 23209-02 09/21/06 advance information 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent dam age to the device. this is a stress rating only and functiona l operation of the device at these or any other conditions above those indicated in the operating section of this specification i s not implied. exposure to absolute maximum rating cond itions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.5 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -40 to +85 o c soldering temperature and time t solder 240 o c, 10sec(lead only) o c operating characteristics (ove r specified temperature range) item symbol test conditions min. typ 1 1. typical values are measured at vcc=vcc typ., t a =25c and not 100% tested. max unit core supply voltage v cc 1.4 1.8 2.3 v i/o supply voltage v ccq v ccq > or = v cc 1.4 1.8 3.6 v data retention voltage v dr chip disabled 3 1.2 v input high voltage v ih v ccq -0.6 v ccq +0.3 v input low voltage v il ?0.3 0.6 v output high voltage v oh i oh = 0.2ma v ccq ?0.2 v output low voltage v ol i ol = -0.2ma 0.2 v input leakage current i li v in = 0 to v cc 0.1 a output leakage current i lo oe = v ih or chip disabled 0.1 a read/write operating supply current @ 1 s cycle time 2 2. this parameter is specified with the out puts disabled to avoid external loading effect s. the user must add current required t o drive output capacitance expected in the actual system. i cc1 v cc =2.3 v, v in =v ih or v il chip enabled, i out = 0 1.5 2.5 ma read/write operating supply current @ 85 ns cycle time 2 i cc2 v cc =2.3 v, v in =v ih or v il chip enabled, i out = 0 10.0 13.0 ma page mode operating supply current @ 85 ns cycle time 2 (refer to power savings with page mode operation diagram) i cc3 v cc =2.3 v, v in =v ih or v il chip enabled, i out = 0 3.5 ma read/write quiescent operating sup- ply current 3 3. this device assumes a standby m ode if the chip is disabled (ce1 high or ce2 low). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss. i cc4 v cc =2.3 v, v in =v ih or v il chip enabled, i out = 0, f = 0 0.2 a standby current 3 i sb1 v in = v cc or 0v chip disabled t a = 85 o c, v cc = 2.3 v 0.2 20.0 a data retention current 3 i dr v cc = 1.8v, v in = v cc or 0 chip disabled, t a = 85 o c 0.1 1.0 a
stock no. 23209-02 09/21/06 advance information 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information power savings with page mode operation (we = v ih ) note: page mode operation is a method of addressing the sram to save operating current. the internal organization of the sram is optimized to allow this unique operating mode to be used as a valuable power saving feature. the only thing that needs to be done is to address the sram in a manner that the internal page is left open and 8-bit words of data are read from the open page. by treating addresses a0-a3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power srams. page address (a4 - a17) oe ce1 ce2 word address (a0 - a3) open page word 1 word 2 word 16 ...
stock no. 23209-02 09/21/06 advance information 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc output load cl = 30pf operating temperature -40 to +85 o c timing v ccq > or = v cc item symbol v cc = 1.4 - 2.3 v v cc = 1.7 - 2.3 v units min. max. min. max. read cycle time t rc 150 85 ns address access time t aa 150 85 ns chip enable to valid output t co 150 85 ns output enable to valid output t oe 50 40 ns chip enable to low-z output t lz 20 10 ns output enable to low-z output t olz 20 5 ns chip disable to high-z output t hz 030015ns output disable to high-z output t ohz 030015ns output hold from address change t oh 20 10 ns write cycle time t wc 150 85 ns chip enable to end of write t cw 75 50 ns address valid to end of write t aw 75 50 ns write pulse width t wp 50 40 ns address setup time t as 00ns write recovery time t wr 00ns write to high-z output t whz 30 15 ns data to write time overlap t dw 50 40 ns data hold from write time t dh 00 ns end write to low-z output t ow 10 5 ns
stock no. 23209-02 09/21/06 advance information 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information timing of read cycle (ce1 = oe = v il , we = ce2 = v ih ) timing waveform of read cycle (we =v ih ) address data out t rc t aa t oh data valid previous data valid address lb#, ub# oe# data valid t rc t aa t co t hz(1,2) t ohz(1) t lbhz, t ubhz t olz t oe t lz(2) high-z data out t lb, t ub t lblz, t ublz ce1# ce2
stock no. 23209-02 09/21/06 advance information 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information timing waveform of write cycle (we control) timing waveform of write cycle (ce1 control) address data in ce1# ce2 lb#, ub# data valid t wc t aw t cw t wr t whz t dh high-z we# data out high-z t ow t as t wp t dw t lbw , t ubw address we# data valid t wc t aw t cw t wr t dh lb#, ub# data in high-z t as t wp t lz t dw t lbw , t ubw data out t whz ce1# (for ce2 control, use inverted signal)
stock no. 23209-02 09/21/06 advance information 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information ball grid array package 32-lead stsop-i package (n32)44- lead tsop ii package (t44) 8 mm 6 mm 0.75 mm 0.75 mm bottom view 18.41mm 10.16mm 0.80mm ref
stock no. 23209-02 09/21/06 advance information 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04m1618l1a ami semiconductor, inc. advance information ordering information ? 2006 ami semiconductor, inc. all rights reserved. ami semiconductor, inc. ("amis") reserves the right to change or modify the information contained in this data sheet and the pr oducts described therein, without prior notice. amis does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. amis makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does amis assume an y liability arising out of t he application or use of any product or circuit described herein. amis does not authorize use of its products as critical components in any application in which the failure of the amis product may be expected to result in significant injury or death, incl uding life support systems and critical medical instruments. revision history revision # date change description 01 11/01/02 initial release 02 9/21/2006 converted to ami semiconductor n04m1618l1ax -xx x i = industrial, -40c to 85c 85 = 85ns @ 1.7v t = 44-pin tsop ii b = 48-ball bga w = known good die - wafer form temperature performance package type
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